CAN Bus Guide

CAN Bus Guide – Dominant And Recessive Bus Level

A Comprehensible Guide to Controller Area Network (CAN Bus) by Wilfried Voss
Click on image for Table of Content

Before going into the details of each bit in a CAN frame it is helpful to have a brief look ahead into the physical layer (For more details refer to Chapter 9 - Physical Layer) in order to understand the nature of, for instance, the SOF (Start of Frame) bit, the RTR (Remote Transmission Request) bit and, in a later chapter, the bus arbitration.

As its name clearly implies, the SOF bit signals the beginning of a message frame. The RTR bit separates the data from the remote frame. Understanding the dominant and recessive level on the CAN bus makes it easier to understand the differentiation between data and remote frame.

The dominant level (TTL = 0V) always overrides a recessive level (TTL = 5V), which is important especially during bus arbitration.

As demonstrated in picture 4.1.1 the CAN bus level will be dominant in case any number of nodes in the network output a dominant level. The CAN bus level will only be recessive when all nodes in the network output a recessive level.

CAN Node Output and Bus Level
Picture 4.1.1: CAN Node Output and Bus Level

The physical CAN bus uses a differential voltage between two wires, CAN_H and CAN_L. A CAN controller with its TTL output uses an additional line driver (transceiver) to provide the standard CAN level (see Chapter 9 - Physical Layer). The following chapters on the CAN frame architecture and bus arbitration refer to the TTL output of the CAN controller.[1]

An equivalent from some electronics basics will explain the relationship between node output and the resulting bus level as shown in picture 4.1.2.

Open Collector Principle on a CAN bus

Picture 4.1.2: Open Collector Principle on a CAN bus
This example uses three nodes in a CAN network, in this case represented by three transistors in open-collector (“Wired And”) configuration. The bus level will be at low level (dominant) in case any number of transistors in the network output a dominant level. The bus level will only be at high level (recessive) when all transistors in the network output a recessive level.

A B C Bus
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Table 4.1.1: Wired And

The following picture demonstrates the transition from an idle CAN bus to an SOF (Start of Frame), meaning the initiation of a new message transfer.

Bus Level and Node Level
Picture 4.1.3: Bus Level Example
Picture 4.1.3 shows the output signal of a CAN node in comparison with the actual bus level.

While the bus is idle, i.e. no node attempts a transmission, the bus will remain on the recessive level.

When one or more nodes attempt to start a transmission they will output the SOF (Start of Frame) bit to the bus. An active SOF bit is per definition at dominant level; therefore an active SOF bit will set the bus to the dominant level.

The bus arbitration mechanism will decide which of the nodes requesting bus access will succeed (refer to Chapter 6 - Bus Arbitration).

The example as shown in picture 4.1.3 demonstrates the transmission of a data frame, which is indicated by a dominant RTR (Remote Transmission Request). A recessive RTR bit would indicate the presence of a remote frame, a frame requesting data from another node.

In theory the data frame in picture 4.1.3 could be the response to a remote frame. The remote frame and the requested data frame use the same message identifier (see also Chapter 4.4 - Remote Frame). The RTR bit, like the message ID, is part of the arbitration field.

A dominant RTR (Remote Transmission Request) bit, indicating a Data Frame, will override a recessive RTR bit (indicating a Remote Frame). As a result, in case that a Remote and Data Frame with the same message ID try to access the bus, the Data Frame will have higher priority than the Remote Frame requesting the data.

[1] Most works on Controller Area Network fail to mention this little, but nevertheless very important fact before they refer to CAN frames, which may lead to the incorrect perception that CAN_L is the dominant level and CAN_H is the recessive bus level.